• Tanisha Tomar
• Mr. Rajesh Parihar

Adders are used in processors in the arithmetic logic units, to calculate addresses, table indices, and other similar operations. Half Adders are frequently required in VLSI(Very Large Scale Integration) from processors to application specific integrated circuits (ASICs). The speed and power dissipation are the important parameters which should be taken into consideration in digital circuits. In this paper, proposed 1 bit half adder is implemented in 180 nm technology at 1.8 V using GDI(Gate Diffusion Input) technique which shows better results in comparison to previous half adders. The proposed half adder is also simulated in 130 nm and 90 nm technology using GDI technology at 1.2V and 0.9V respectively. Power consumption, propagation delay, Power Delay Product and Energy Delay Product are compared and analyzed.

Very large scale integration, Adders, Power dissipation

"Implementation of low power half adder in GDI technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 6, page no.535-540, June-2018, Available :http://www.jetir.org/papers/JETIR1806201.pdf

"Implementation of low power half adder in GDI technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 6, page no. pp535-540, June-2018, Available at : http://www.jetir.org/papers/JETIR1806201.pdf