UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 5 Issue 7
July-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1807508


Registration ID:
185086

Page Number

294-301

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Title

A Cost-Efficient Improved VLSI Architecture for Buffer-less Edge-Oriented Demosaicking

Abstract

Color filter array interpolation in addition spoken as demosaicking and ‘debayering’, is also an important technique for image reconstruction in digital still cameras. This paper presents an edge-oriented demosaicking technique and an inexpensive very-large-scale integration (VLSI) style for color interpolation. the planning uses easy operations (addition, subtraction, shift, and comparator) and nearest neighboring pixels to catch the color distinction and edges. the required line buffering of the projected vogue is four lines; therefore, its hardware value is low. Our intensive experiments disclosed that the projected technique preserved edge options and exhibited superb qualitative analysis and visual quality performances. Compared with the previous VLSI implementations, the projected vogue achieved superior image qualities. The synthesis results disclosed that by exploitation Taiwan Semiconductor manufacturing Company zero.18-μm technology the projected style yields a process rate of roughly two hundred M samples per second.

Key Words

Color filter array (CFA) interpolation, demosaicking, pipeline architecture, very-large-scale integration (VLSI).

Cite This Article

"A Cost-Efficient Improved VLSI Architecture for Buffer-less Edge-Oriented Demosaicking", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.294-301, July-2018, Available :http://www.jetir.org/papers/JETIR1807508.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"A Cost-Efficient Improved VLSI Architecture for Buffer-less Edge-Oriented Demosaicking", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp294-301, July-2018, Available at : http://www.jetir.org/papers/JETIR1807508.pdf

Publication Details

Published Paper ID: JETIR1807508
Registration ID: 185086
Published In: Volume 5 | Issue 7 | Year July-2018
DOI (Digital Object Identifier):
Page No: 294-301
Country: Bengaluru, Karnataka, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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