• Meghana PA
• Dr. Ramesh S

In this paper design & synthesize of Reversible PROM, half adder/subtracter & full adder/subtracter using reversible decoder logic is presented. Reversible logic is an emerging technology in the field of research in present era. The PROM Programmable Read Only Memory device which consists of fixed AND Gates and programmable OR gates array is one of the type of the simple PLD with n input and k output (referred as (n, k)) is said to be reversible if and only if the number of inputs is equal to number of outputs. The input pattern maps the output pattern uniquely. The reversible logic must run both forward and backward in such a way that the inputs can also be retrieved from outputs. The designed circuits are analyzed in terms of delay, quantum cost, garbage outputs and number of gates. The Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN6.

PROM, Decoder, Adder/subtracter, Quantum Cost, Reversible Gates, Garbage Outputs, Number of gates,FPGA.

"DESIGN AND FPGA IMPLEMENTATION OF REVERSIBLE PROGRAMMABLE READ ONLY MEMORY, ADDER & SUBTRACTER USING REVERSIBLE DECODER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.902-912, July-2018, Available :http://www.jetir.org/papers/JETIR1807592.pdf

"DESIGN AND FPGA IMPLEMENTATION OF REVERSIBLE PROGRAMMABLE READ ONLY MEMORY, ADDER & SUBTRACTER USING REVERSIBLE DECODER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp902-912, July-2018, Available at : http://www.jetir.org/papers/JETIR1807592.pdf