• NEKKANTI LAKSHMI INDIRA RANI
• NADAVAPALLI GAYATRI

The main objective of this project is to implement a novel processor for small-scale (minor) and large-scale (major) applications with low dense and low power consumption. In this, well-tuned pipelined architecture and enhanced power control schemes are introduced using modified MIPS (Micro Processor without Inter locked stages), VLIW (Very Long Instruction Word) and PFAL (Positive feed Back Adiabatic Logic) techniques along with BIST (Built in Self-Test) capability. Online and more accurate BIST is implemented with less processing time. This project is designed in such a way that; it is useful for both long and short distance; wired and wireless communications for both Synchronous and Asynchronous modes.

BIST, VLIW, PFAL, L.F.S.R (Linear Feed Back Shift Register), GALS (Global Asynchronous Local Synchronous), ILP (Instruction Level Parallelism)

"POWER OPTIMIZED CRUSOE PROCESSOR WITH REVERSIBLE LOGIC GATES USING ENHANCED VLIW ARCHITECTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.575-581, August-2018, Available :http://www.jetir.org/papers/JETIR1808084.pdf

"POWER OPTIMIZED CRUSOE PROCESSOR WITH REVERSIBLE LOGIC GATES USING ENHANCED VLIW ARCHITECTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp575-581, August-2018, Available at : http://www.jetir.org/papers/JETIR1808084.pdf