UGC Approved Journal no 63975(19)

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Published in:

Volume 5 Issue 8
August-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1808243


Registration ID:
186467

Page Number

634-643

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Title

Design of a Low Complexity Fault Tolerant Parallel FFT Using The Parity-SOS-ECC Technique

Abstract

Delicate mistakes emerge because of CMOS scaling in a few electronic circuits. Delicate mistakes are no exemption to the correspondence and flag handling frameworks. These blunders can be recognized and redressed by some algorithmic-based adaptation to non-critical failure (ABFT) procedures. One of them is the Fast Fourier Transform (FFTs) is a key building hinder in many flag handling frameworks. Numerous strategies have been proposed to identify and amend blunders in FFTs. Among those one of them is the Parseval check or entirety of squares strategy which is generally known. A few pieces are working in parallel for some correspondence frameworks. As of late, a strategy that adventures to actualize adaptation to non-critical failure on parallel channels has been proposed. In this paper two insurance systems have been proposed in that parseval check is utilized to recognize numerous blame FFTs however revises just single mistake at once. The second method is the equality SOS-ECC blame tolerant parallel FFTs strategy is utilized to lessen the quantity of SOS checks required. The second strategy likewise used to identify and rectify single mistake at once because of this it has the drawback of time delay. The proposed system investigations the rationale estimate, zone, postponement and power utilization utilizing Xilinx 12.2.

Key Words

Error Correction Codes (ECCs), Fast Fourier Transforms (FFTs), Soft Errors...

Cite This Article

"Design of a Low Complexity Fault Tolerant Parallel FFT Using The Parity-SOS-ECC Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.634-643, August-2018, Available :http://www.jetir.org/papers/JETIR1808243.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design of a Low Complexity Fault Tolerant Parallel FFT Using The Parity-SOS-ECC Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp634-643, August-2018, Available at : http://www.jetir.org/papers/JETIR1808243.pdf

Publication Details

Published Paper ID: JETIR1808243
Registration ID: 186467
Published In: Volume 5 | Issue 8 | Year August-2018
DOI (Digital Object Identifier):
Page No: 634-643
Country: -, -, -- .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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