• Suman Rani
• Amandeep Singh Bhandari

A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design. In this work, a reversible 6 bit reversible unsigned square root is proposed using modified restoring algorithm. In this design we try to reduce optimization parameters like power consumption and quantum cost. The experimental results obtained for implementation in Xilinx ISE 14.2 shows the considerable reduction in terms of Quantum Cost & Power consumption in comparison with the existing design using conventional gates.

Low Power digital design, Reversible Logic, Floating-point square root, Power Consumption.

"Design of a Reversible 6-bit Reversible Unsigned Square Root using Modified Restoring Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.396-401, August-2018, Available :http://www.jetir.org/papers/JETIR1808358.pdf

"Design of a Reversible 6-bit Reversible Unsigned Square Root using Modified Restoring Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp396-401, August-2018, Available at : http://www.jetir.org/papers/JETIR1808358.pdf