• D.Habeeba Sulthana
• Dr. S.Vijay Kumar

Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. It’s simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as "Urdhva Tiryagbhayam multiplier”. The Urdhva Tiryagbhayam literally means .This will be implemented using reversible logic. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications The purpose of this project is to implement a 16x16 Vedic multiplier using reversible gates which are operated at very high speed. The functionality of RT is verified by using Xilinx 14.5.

Urdhva Tiryagbhayam, Multipliers.

"AN EFFICIENT IMPLEMENTATION OF HIGH SPEED, LOW POWER VEDIC MULTIPLIERS USING REVERSIBLE GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.69-73, September-2018, Available :http://www.jetir.org/papers/JETIR1809160.pdf

"AN EFFICIENT IMPLEMENTATION OF HIGH SPEED, LOW POWER VEDIC MULTIPLIERS USING REVERSIBLE GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp69-73, September-2018, Available at : http://www.jetir.org/papers/JETIR1809160.pdf