• LAXMISAGAR HS
• Vinutha B

Embedded systems have drastically grown in importance and complexity in recent years. Many systems are now designed using Field Programmable Gate Array (FPGA) due to its size, flexibility, and resources. The main aim of this project is to design and verify APB-compliant Quad channel UART (Universal Asynchronous Receive Transmit) with random skew suitable for use in embedded systems and System on Chip (SoC).The QUAD-UART design proposed in this implementation has a single Host interface; this was not a feasible solution. Hence, what was attempted was to introduce an arbitrary (Radom) skew while looping back from Transmitter to Receiver. This skewed loop-back still verifies the “Asynchronous” behaviour of the UART.

APB, AMBA

"Design and Verification of APB Compliant Quad Channel UART with arbitrary random skew ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.174-181, September-2018, Available :http://www.jetir.org/papers/JETIR1809331.pdf

"Design and Verification of APB Compliant Quad Channel UART with arbitrary random skew ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp174-181, September-2018, Available at : http://www.jetir.org/papers/JETIR1809331.pdf