• Archana Baghel
• Shweta Agrawal

A fast and power-proficient CMOS full Adder (FA) assumes enter part in gadgets exchange particularly performing math tasks in microchips, digital signal processing (DSP) what's more, image processing. Full Adder (FA) is such a noteworthy component which contributes generously to the aggregate power utilization of the system. In this paper, topologies of CMOS Full Adder has been delineated which is then penniless down. The leakage power utilization has been done in the circuit utilizing diverse topologies, for example, 90nm and 45nm. By using Cadence tools, the designed CMOS Full adder Topologies are compared in phrases of leakage power consumption and surface area. We planned and thought about 14T CMOS full adder, 12T CMOS full adder 10T full viper and 9T CMOS full adder as far as zone, power

CMOS, CMOS Full Adder, Leakage Power, Leakage Current, Area, Cadence

"Design and Simulation of Different Topology of Low Power CMOS Full Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.535-540, September-2018, Available :http://www.jetir.org/papers/JETIR1809389.pdf

"Design and Simulation of Different Topology of Low Power CMOS Full Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp535-540, September-2018, Available at : http://www.jetir.org/papers/JETIR1809389.pdf