• Dr.S.Aruna
• K.Mounika
• K. Srinivasa Naik

In low power VLSI circuit designs, the leakage power reduction plays an important role. The scaling down of threshold voltage has contributed vastly towards increase in sub threshold leakage current thereby making the static (leakage) power dissipation very high. Due to the leakage power the battery operated devices with long duration in standby mode may be drained out very quickly. In this work, high performance and low power ONOFIC approach have been implemented for VLSI CMOS (Complementary Metal Oxide Semiconductor) circuits. Many techniques have been proposed for reducing leakage current in deep submicron but with some limitations they are not suitable for actual requirements. Here discuss three techniques named CMOS, LECTOR (LEakage Control TransistOR) and ONOFIC (On/Off logic). In this work, 8-bit magnitude comparator is designed by three techniques and compare the power dissipation and performance among CMOS, LECTOR and ONOFIC. The tool which is used for implementing the design is Tanner EDA V15.0.

Leakage current, ONOFIC, LECTOR, deep submicron.

"High Performance and Low Power VLSI CMOS 8-Bit Magnitude Comparator Circuit Design Using ONOFIC Approach", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 11, page no.107-119, November-2018, Available :http://www.jetir.org/papers/JETIR1811617.pdf

"High Performance and Low Power VLSI CMOS 8-Bit Magnitude Comparator Circuit Design Using ONOFIC Approach", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 11, page no. pp107-119, November-2018, Available at : http://www.jetir.org/papers/JETIR1811617.pdf