• Khyati Sharma
• Shweta Agrawal

In this paper, we demonstrate a low power high speed 2:1 MUX design using a Static CMOS logic and Pseudo NMOS logic at 180nm, 90nm and 45nm a technology. In order to suppress the degradation of signals and to increase the operation speed, we designed interconnection for the circuit; the implementation is done in VLSI technology as it has features like small size, low cost, high operating speed and low power. The circuit shows rise and fall times of about 1ns and consumes low power according to the design and number of transistor used in the circuits. The static CMOS logic and pseudo NMOS logic based 2:1 MUX is the most efficient design because the average power consumption is low and reduced leakage current. The designed circuits is realized in a standard 180nm, 90nm and 45nm process technology and uses 1.8V, 0.7V and 0.7V supply voltage. Our optimization circuitry using the proposed method reduces power consumption and leakage current by significant amount of multiplexer circuit.

: MUX, Pseudo NMOS logic Low Power, Static CMOS logic, Pseudo NMOS logic Low Power, Leakage Current, Cadence.

"Design and Simulation of 2:1 MUX using Various CMOS logic at different level of Technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.332-341, December-2018, Available :http://www.jetir.org/papers/JETIR1812447.pdf

"Design and Simulation of 2:1 MUX using Various CMOS logic at different level of Technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp332-341, December-2018, Available at : http://www.jetir.org/papers/JETIR1812447.pdf