• Divya Sharma
• Shweta Agrawal

This research paper analyzes the performance of De-Multiplexer (DEMUX) using CMOS based DEMUX, Pass Transistor based DEMUX. Moreover, an evaluation among the exhibitions of both the setups as far as power dissemination, chip region, power supply and leakage current are evaluated. In order to restrain the deprivation of signals and to increase the operation speed, we designed interconnection for the circuit; the implementation is done in VLSI technology as it has features like small area, low cost, reduction in leakage current and low power. The circuit shows rise and fall times of about 1ns and consumes low power according to the design and number of transistor used in the circuits. The composed circuit is acknowledged in a standard 90nm and 45nm process technology and utilizations 0.7V supply voltage. Our optimization circuitry using the proposed method reduces power consumption and leakage current by significant amount of DEMUX circuit.

DEMUX, CMOS Based DEMUX, Pass Transistor Based DEMUX Low Power, Leakage Current, Cadence.

"Design and Performance Comparisons of CMOS based and Pass Transistor based 1:2 DEMUX at 90nm and 45nm Technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.342-349, December-2018, Available :http://www.jetir.org/papers/JETIR1812448.pdf

"Design and Performance Comparisons of CMOS based and Pass Transistor based 1:2 DEMUX at 90nm and 45nm Technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp342-349, December-2018, Available at : http://www.jetir.org/papers/JETIR1812448.pdf