• Shilpi dubey
• Pankaj Shrivastava

The majorobjective of this paper is to propose a low power 8x8 SRAM array utilize7T SRAM cell.High-density SRAMs employinsistentlyminiature bit-cells that are focus to tremendous inconsistencycorrupting their read and write-current. SRAM is a crucialfunction in varieties of purposesuch as cache memories, microprocessors and portable devices. If technology’s node scaling fall, leakage power is the maintrouble in SRAM cell disturbed for the less power application. So, there is a requirement of low power adequate memory design. The futuredesign of 8x8 SRAM array is comparable to 8x8 SRAM array exploitconservative 6T SRAM cell, justsingleadditional NMOS transistor is locatedamong two cross coupled inverter. This architecture decrease static power in support mode. Cadence imitationinstrument is utilized at 90nm expertise for scheming. Relativestudy is presented in order of Leakage power consumption, Read Access time, Write Access time and Absolute Leakage power consumption. Tangentialapparatus of inclusive 8x8 SRAM array has been intendedlike SRAM cell, row /column decoder and sense amplifier.

CMOS, SRAM, 7T SRAM Cell, Leakage Power,Cadence.

"Implementation and Analysis of 8x8 Array using 7T SRAM Cellfor Low power CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.371-379, December-2018, Available :http://www.jetir.org/papers/JETIR1812451.pdf

"Implementation and Analysis of 8x8 Array using 7T SRAM Cellfor Low power CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp371-379, December-2018, Available at : http://www.jetir.org/papers/JETIR1812451.pdf