• Nishtha Deora
• Pankaj Shrivastava

Low power VLSI system, Static random access memory (SRAM) is crucial circuits.In this paper leakage current and leakage power of conventional 6T cell at90nm technology has been estimated and circuit techniques to reduce Leakage in deep sub micronlike Sizing of transistor & Power Gating has converse&functional on conventional 6T SRAM cell. By sizing of transistors in 6T SRAM cell an optimized 6TCache memory cell is attain&evaluated&set up for additionalcapable than conventional 6T SRAM Cell. Afterthat Power Gatingis applied on the optimized 6TSRAM cache memory Cell and it is establish to be most efficient interms of leakage current and leakage power&develop speed of circuit.

SRAM 6T Cell, Leakage Power Leakage Current, Power Gating, Cadence tool

"Performance and Analysis ofResilient 6T SRAM cell For Low Leakage and high speed CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.380-394, December-2018, Available :http://www.jetir.org/papers/JETIR1812452.pdf

"Performance and Analysis ofResilient 6T SRAM cell For Low Leakage and high speed CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp380-394, December-2018, Available at : http://www.jetir.org/papers/JETIR1812452.pdf