• Rashmi KM
• Dr..k.N. Muralidhara
• Raghuveera Pandith

Abstract— Time, power and test data volume are among some of the challenging issues for testing the VLSI systems and have not been fully resolved. The power and energy may increase significantly during testing, this extra power consumption may give rise sever hazards to the circuit reliability and effectively increases the test cost and time. Scan chain masking is a technique which makes the testing of the digital circuits easier by providing simple method to observe each and every flip-flops in the design. When Flip-Flops are connected in series forms a Scan chain and when two or more Scan chains in a single compactor forms complexity in diagnosis the integrated circuits. In this paper diagnosis of multiple failures in multiple Scan chains were proposed. The strategy mainly focused on test time reduction, power reduction during testing.

Automatic Test Equipment(ATE); masking ; Scan chain diagnosis; test response compaction; test data compression.

"EFFICIENT SCAN CHAIN MASKING AND RE-ORDERING FOR DIAGNOSIS OF MULTIPLE FAULTS IN VLSI CIRCUITS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.29-36, December-2018, Available :http://www.jetir.org/papers/JETIR1812606.pdf

"EFFICIENT SCAN CHAIN MASKING AND RE-ORDERING FOR DIAGNOSIS OF MULTIPLE FAULTS IN VLSI CIRCUITS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp29-36, December-2018, Available at : http://www.jetir.org/papers/JETIR1812606.pdf