• PRIYANKA RESHMIYA
• K. S. SOLANKI

Abstract: As we know the leakage power is very important and these is increasing when we going from one technology to another technology generation. CMOS technology improved the level of performance which providing good characteristics such as low cost, low discharge, low power dissipation, high density, low leakage current in the circuits. DRAM used as a cache memory due to the volatile in nature. So that we need to refresh the circuitry and which providing the problem of the leakage current and power consumption. Which can be overcome by proceeding the implementation of DRAM with self-voltage level controllable technique (SVLC). This can be done by using DSCH and Microwind software. This technique help to reduce the leakage current at the lowest point.

SVCL,DRAM,LEAKAGE CURRENT,POWER CONSUMPTION

"SVCL BASED 4T DRAM DESIGN WITH REDUCTION LEAKAGE CURRENT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.89-93, January-2019, Available :http://www.jetir.org/papers/JETIR1901714.pdf

"SVCL BASED 4T DRAM DESIGN WITH REDUCTION LEAKAGE CURRENT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp89-93, January-2019, Available at : http://www.jetir.org/papers/JETIR1901714.pdf