UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 12 | Issue 9 | September 2025

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Published in:

Volume 6 Issue 2
February-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1902072


Registration ID:
195067

Page Number

541-544

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Title

FPGA Implementation of Low Power Secure Hashing Algorithm (SHA-2) using VHDL.

Abstract

Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. The hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge. Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. Cryptography plays an important role in the security of data. Even though the data is encrypted it can be altered while transmitting on the network so data should be verified using a digital signature. Hashing algorithms are used to create these digital signatures for verification of the data received. Hashing algorithm like Secure Hash Algorithm-2 (SHA-2(224/256)) is designed which has a fixed output length of 512-bits.

Key Words

FPGA Implementation of Low Power Secure Hashing Algorithm (SHA-2) using VHDL.

Cite This Article

"FPGA Implementation of Low Power Secure Hashing Algorithm (SHA-2) using VHDL.", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.541-544, February-2019, Available :http://www.jetir.org/papers/JETIR1902072.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"FPGA Implementation of Low Power Secure Hashing Algorithm (SHA-2) using VHDL.", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp541-544, February-2019, Available at : http://www.jetir.org/papers/JETIR1902072.pdf

Publication Details

Published Paper ID: JETIR1902072
Registration ID: 195067
Published In: Volume 6 | Issue 2 | Year February-2019
DOI (Digital Object Identifier):
Page No: 541-544
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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