• Amol Nagawade

Emerging multicore processors are progressively power guarded by design ambiguity due to process dissimilarities. With the help of dynamic voltage scaling energy consumption can be reduced in microprocessor can be achieved without affecting the peak performance. In handy electronic devices processors are having a average load which is having a time-varying performance requirement. A methodology to vary DVS is by varying supply voltage of the processor’s so that it ingests the least amount of energy by operating at the lowest performance level required by the dynamic software processes. It is a key method in developing the hardware characteristics of processors to decrease energy dissipation by dropping the operating frequency and supply voltage. To meet energetically varying performance requirement the method varies the voltage of processor below software control. The DVS algorithm are shown to be proficient to make dramatic energy storing while providing the essential peak average power in general purpose systems

FPGA, DVS, VCO, VHDL, Xilinx.

"Dynamic Voltage Scaling Using FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.652-656, February-2019, Available :http://www.jetir.org/papers/JETIR1902789.pdf

"Dynamic Voltage Scaling Using FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp652-656, February-2019, Available at : http://www.jetir.org/papers/JETIR1902789.pdf