• Rekha sand
• Dr.A.M.Bhavikatti

In the keep going couple of rot, Network on Chip's (NoC) are the ground-breaking chips for fast correspondences relating to 802.11 Ethernet convention which is a should be reconfigurable for fruitful information outline transmission. The current models like coarse grained reconfigurable, ALU group and articulation grain reconfigurable engineering and look-into table utilized in fine grained reconfigurable gadgets requires a great deal of capacity memory, equipment assets, for example, cuts, cell region and cell delay. To handle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their execution examination parameters are determined. The MRPMA utilizes the four commitments to improve Processing Elements (PE's) tasks: 1) Fast Fourier Transformation (FFT) to perform settled direct numbers toward the design words, 2) Discrete Cosine Transformation (DCT) to investigate the information in the recurrence space, 3) Finite Impulse Response (FIR) for parallel mapping the information and 4) Channel encoder and decoder to encode the information and to ascertain the most limited course from source to destination switch.

FFT, DCT, FIR, Channel encoder, FPGA, MRPMA, NoC

"FPGA Based design and Implementation of NoC through Multigrained Reconfiguration and Parallel Mapping for multi DSP applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.418-427, February-2019, Available :http://www.jetir.org/papers/JETIR1902860.pdf

"FPGA Based design and Implementation of NoC through Multigrained Reconfiguration and Parallel Mapping for multi DSP applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp418-427, February-2019, Available at : http://www.jetir.org/papers/JETIR1902860.pdf