• Lokesh Kumar
• Amit Kumar

In the technology of nanotechnology, excessive overall performance feature is embedded into small scale tool. As the technology is improving into micro scale to deep submicron scale, and the transistor size is cut back. As the end result power intake, signal energy, speed and tool length minimizing are predicament undertaking. Generally chip encompass a million of transistor. So a lots of parameters optimization related to transistor together with strength dissipation is take care for circuit synthesis.

CMOS, Power Dissipation, Novel Sleep, Transistor.

"A Review on Low power efficiency of Novel Sleep Transistor on 180nm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.430-434, March-2019, Available :http://www.jetir.org/papers/JETIR1903360.pdf

"A Review on Low power efficiency of Novel Sleep Transistor on 180nm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp430-434, March-2019, Available at : http://www.jetir.org/papers/JETIR1903360.pdf