UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 12 | Issue 9 | September 2025

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Published in:

Volume 6 Issue 3
March-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1903707


Registration ID:
200802

Page Number

42-43

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Title

Modelling of discrete events using Verilog language

Abstract

Design is a complex process which can be thought of as a top down refinement of a specification. The main aim of this algorithm is to propose a VHDL code generator for real-time systems. Its importance lies in giving graphical interface to the designer. Here, a discrete event model for a digital circuit using VHDL is designed and implemented.

Key Words

Modelling of discrete events using Verilog language

Cite This Article

"Modelling of discrete events using Verilog language ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.42-43, March-2019, Available :http://www.jetir.org/papers/JETIR1903707.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Modelling of discrete events using Verilog language ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp42-43, March-2019, Available at : http://www.jetir.org/papers/JETIR1903707.pdf

Publication Details

Published Paper ID: JETIR1903707
Registration ID: 200802
Published In: Volume 6 | Issue 3 | Year March-2019
DOI (Digital Object Identifier):
Page No: 42-43
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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