• Sanjeeda syed
• S.Asif Ahamad
• C.R.Gowthami
• T.Mahaboob Basha
• S.Janardhan

low power efficient digital devices are target of researchers in recent years. This paper proposes the design of a low power high speed, energy efficient full adder, full subtractor, 2 bit comparator using MGDI technique the entire design has been performed in technology the n these digital circuits were compared with traditional CMOS transistors in terms of power dissipation , number of transistors, area ,speed, and delay .the simulation of the proposed design has been carried out in DSCH2 and the layout has been designed in micro wind

GDI CELL, MGDI CELL, Adder-Subtractor, Comparator, Power consumption.

" A Novel Approach for Design of 8-Bit Adder-Subtractor and Comparator Using MGDI Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.90-96, March-2019, Available :http://www.jetir.org/papers/JETIR1903J15.pdf

" A Novel Approach for Design of 8-Bit Adder-Subtractor and Comparator Using MGDI Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp90-96, March-2019, Available at : http://www.jetir.org/papers/JETIR1903J15.pdf