• Harish Kumar K
• Dhanasekar S
• Jayakumar R
• Ajin R

Some high performance systems like digital signal processors (DSP), microprocessors, FIR filters etc. uses barrel shifters, multipliers, multiplexers, delay elements as key components. Performance of the multiplier determines the system’s performance. Multipliers are very slow and also consume most of the area in the system. Hence, optimization of speed and area are major constrains in the design of multiplier. Least Mean Squared (LMS) algorithm benefits as low convolution and coherence of implementation. One main concern in all experimental situations is to develop stemmer that provide faster convergence of the adaptive filter by the instant better filtering performance. A better architecture for the implementation of a DLMS adaptive filter to achieve low adaptation-delay and efficient area, we propose the use of a novel partial product generator and a scheme for optimized balanced pipelining across the time-consuming combinational blocks. This have less area-delay product (ADP) and less energy-delay product (EDP) than the best of the existing systolic structures, on average, for N = 8, 16, 32 and 64.We propose an efficient fixed-point implementation scheme of the proposed architecture, and thereby replacing shift adder tree by carry select adder.

Adaptive filters, fixed-point arithmetic, least mean square (LMS) algorithm

"Area Efficient Fixed-Point LMS Adaptive Filter ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.65-70, April-2019, Available :http://www.jetir.org/papers/JETIR1904309.pdf

"Area Efficient Fixed-Point LMS Adaptive Filter ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp65-70, April-2019, Available at : http://www.jetir.org/papers/JETIR1904309.pdf