• GAJULA.DEVI PRASANNA
• YARRABAPU.GANESH KUMAR
• JAMPALA.VENKATA JHANSI
• PABATHULA. MADHAVA RAO

Field programmable gate arrays (FPGAs) are progressively utilized as the registering stage for quick and vitality effective execution of acknowledgment, mining, and inquiry applications. Surmised registering is one promising strategy for accomplishing vitality productivity. Contrasted and earlier chips away at rough registering, which target estimated processors and number juggling squares. Half and half configurable rationale square designs for field programmable entryway exhibits that contain a combination of request tables and solidified multiplexers are assessed toward the objective of higher rationale thickness and zone decrease.

FPGA, Multiplexer logic element, Complex logic block, mapping technologies.

"HIGH LOGIC DENSITY ARCHITECTURES OF FPGA USING HYBRID CLB’S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.480-489, April-2019, Available :http://www.jetir.org/papers/JETIR1904372.pdf

"HIGH LOGIC DENSITY ARCHITECTURES OF FPGA USING HYBRID CLB’S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp480-489, April-2019, Available at : http://www.jetir.org/papers/JETIR1904372.pdf