• Tripti Mahajan

With the advent of very large scale design techniques it is possible to fabricate more transistors. The processors are a major information processing element in all electronic circuits. This paper discusses the structure of multi-cycle low power 32-bit multicycle MIPS processor. The MIPS processor will be designed utilizing HDL. Here, we propose the architecture of multi-cycle pipelined 32-bit Microprocessor. Our processor will have no Interlocked Pipeline Stages (MIPS). This processor is a Reduced Instruction Set Computing (RISC) structure based processor. This processor is configured with multiple stages of the pipeline. These stages include Instruction Fetch (IF), Instruction Decode and Enroll Fetch (ID), Execution& Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules. The fundamental components of the processor are CPU, ALU, Program Counter, Control Unit, MUX, Information Memory, Register File, Sign Extension, Instruction Memory

Microprocessor without Interlocked Pipeline Stages (MIPS), — Reduced Instruction Set Computer (RISC), Complex Instruction Set Computer (CISC), Hardware description languages (HDL), Verilog.

"Low power 32 bit multicycle MIPS processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.418-421, April-2019, Available :http://www.jetir.org/papers/JETIR1904773.pdf

"Low power 32 bit multicycle MIPS processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp418-421, April-2019, Available at : http://www.jetir.org/papers/JETIR1904773.pdf