• A.B.YASWANTH
• N.SATYANARAYANA
• T.MURALI KRISHNA
• M.MADHU MOHAN
• Mr. CH. NAVEEN KUMAR

In This Paper presents novel designs of static dual-edge triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 180 nm CMOS technology and the simulation results done on HSPICE Soft Ware. Finally compare the existing and proposed results in terms of delay and power consumption, design of master slave dual edge triggered flip-flop

"DESIGN AND IMPLEMENTATION OF LOW POWER AND LOW GLITCH FLIP-FLOPS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.572-578, April-2019, Available :http://www.jetir.org/papers/JETIR1904986.pdf

"DESIGN AND IMPLEMENTATION OF LOW POWER AND LOW GLITCH FLIP-FLOPS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp572-578, April-2019, Available at : http://www.jetir.org/papers/JETIR1904986.pdf