• B. SRINIVASA REDDY
• R. NARAYANA
• Y. KAMALA
• G. KESAVA SAI KRISHNA REDDY
• D. GOWRI SANKAR RAO

In Fault tolerant reversible logic gate circuit, the parity of the input vector must equal the parity of the output vector. It renders to find the fault in the circuit. Thus, the parity preserving reversible logic will be beneficial to the development of fault tolerant systems in nanotechnology. Fault tolerant reversible logic and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. This thesis presents an efficient realization of D flip-flop and master slave flip-flop using RR- Fault tolerant parity preserving reversible gates. The minimum power, delay, power delay product and hardware complexity to synthesize a fault tolerant reversible D flip-flop and master slave flip-flop circuit has also been given. Finally, this thesis presents a novel fault tolerant reversible D flip-flop and master slave flip-flop circuit and demonstrates its superiority with the existing.

Reversible gates, RR Gate, MSH Gate, D-Flip-Flop, Master-Slave Flip-Flop.

"HIGH SPEED FAULT TOLERANT FLIP-FLOP USING REVERSIBLE GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.596-606, April-2019, Available :http://www.jetir.org/papers/JETIR1904990.pdf

"HIGH SPEED FAULT TOLERANT FLIP-FLOP USING REVERSIBLE GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp596-606, April-2019, Available at : http://www.jetir.org/papers/JETIR1904990.pdf