• POOJA ZADEY
• prof. Wani patil

This paper presents Low-density parity-check codes as error correcting tool at present. By using LDPC (Low-density parity-check codes) decoder, aim to implement on the FPGA (Field Programmable Gate Array) with less complexity. The main propose of this decoding structure to reduce the complexity with the help of node unit which is check node unit (CNU) and the variable node unit (VNU) employing a min-sum algorithm for getting a good result. Here, we used a multiplexed storage structure for storing node message to get the result in minimum slice resources. This LDPC code is based on the Code scheme in 802.11n standards. Therefore it encodes 324 message bit and creates 648 bit encoded message using AWGN channel to pass the message. Hence this designing stages helps such as encoding, channel Additive White Gaussian Noise (AWGN), and LDPC decoder. Therefore we used here a min-sum algorithm for decoding and encoding bit stream. The low-complexity method becomes a research area to achieve the requirements put in future for wired and wireless communication field. Keywords— LDPC (Low-density parity-check codes) decoder; Low-complexity implementation; Min-Sum algorithm, Additive White Gaussian Noise (AWGN) channel.

Keywords— LDPC decoder; Low-complexity implementation; Min-Sum algorithm.

"Review paper on FPGA implementation of min-sum algorithm for LDPC decoder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.102-106, April-2019, Available :http://www.jetir.org/papers/JETIR1904B17.pdf

"Review paper on FPGA implementation of min-sum algorithm for LDPC decoder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp102-106, April-2019, Available at : http://www.jetir.org/papers/JETIR1904B17.pdf