• Dattaprasad Narayan Golatkar
• Sanjay Babasaheb Patil

The Low power and low energy has become an important issue in today’s consumer electronics. The increasing demand for low-powered devices can be addressed at different design levels, such as the architectural, circuit, layout, and the process technology level. Combinational circuit can be represented as a several input lines with single output line. Multiplexers are used to design any digital combinational logic circuit. Hence it is required to design a multiplexer with low power consumption and high speed. At the circuit design level, considerable potential for power savings exists by means of proper choice of a logic style like CMOS, PTL,TG for implementing combinational circuits. Depending on the application, the kind of circuit to be implemented, and the design technique used, different performance aspects such as transistor count, power dissipation, and delay become important, disallowing the formulation of universal rules for optimal logic styles. This paper presents study about 2:1 and 4:1 multiplexer with Different Techniques and topologies at Nanometer regime.

CMOS, DPTL , FinFET, Power Dissipation, Speed, Transistor Count.

"Design of a Multiplexer in Different Logics at Nanometer Regime- A Review ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.73-78, April-2019, Available :http://www.jetir.org/papers/JETIR1904J06.pdf

"Design of a Multiplexer in Different Logics at Nanometer Regime- A Review ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp73-78, April-2019, Available at : http://www.jetir.org/papers/JETIR1904J06.pdf