• Swati Tukaram Mestry
• Dr. Swati Vijay Sankpal

Multiplier is a core element of Digital signal processor(DSP). The speed of the multipliers affects the speed of the Digital signal processors. The execution of most DSPs is dependent on its multipliers, and hence need for high speed multipliers arises. In this digitization era, it becomes necessary to increase the speed of the digital circuits while reducing on-chip area and memory consumption. For increasing multiplication speed and reducing delay there is more and more emphasis on designing faster multipliers. There are many algorithms like standard modified booth algorithm, Wallace tree methods, vedic multiplier and several new techniques designed to enhance the speed of the multiplier. Among this, algorithms based on Vedic mathematics can be used to design faster and low power multipliers.[4] This paper presents study about different Vedic multipliers with different adders and different technologies used in different papers.

"A Review Paper on Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.59-64, April-2019, Available :http://www.jetir.org/papers/JETIR1904N11.pdf

"A Review Paper on Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp59-64, April-2019, Available at : http://www.jetir.org/papers/JETIR1904N11.pdf