• Shraddha
• Manish Kumar

Scaling down in technology facilitates high performance with less delay, but it also simultaneously increases the power dissipation. Reduction in power dissipation is very crucial because of increasing the demand of battery operated systems and portable devices. Due to scaling down feature of CMOS VLSI circuit, power dissipation is a most challenging issue [1]. The number of transistors is approximately double for every two years [2]. Power dissipation is directly proportional to the square of supply voltage. Scaling down the power supply voltage can significantly reduce the power consumption, but it degrades the performance of the circuit in terms of increased delay. The delay of the circuit is compensated by reducing the threshold voltage of the circuit. Lower threshold voltage in MOS transistors tremendously increases the leakage current. In this paper, first we reviewed a comprehensive survey and analysis of various low power circuit design techniques. The proposed digital circuits are designed by utilizing the merits of DTCMOS (Dual-threshold CMOS), stack and sleepy keeper techniques. The performance of proposed designed circuit is compared in term of power dissipation, delay and power delay product. All simulation are done at a temperature of 27 0 C by using Mentor Graphics Pyxis EDA Tools in 130nm technology.

" Design and Performance Analysis of Low Power Digital Circuits in Nanoscale Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.453-459, April-2019, Available :http://www.jetir.org/papers/JETIR1904N62.pdf

" Design and Performance Analysis of Low Power Digital Circuits in Nanoscale Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp453-459, April-2019, Available at : http://www.jetir.org/papers/JETIR1904N62.pdf