• DAKSHAYANI YANAPU
• Mr.C.VENKATA SUDHAKAR

Canonic signed digit (CSD) involves very few non-zero bits, designing it for high speed and area optimization in VLSI based DSP architectures. The CSD has been designed with number of adders. Because of faults like struck at faults present in the adders during its operation, there may be a deviation in the expected results. It is very difficult to detect these faults in offline. So that, We proposed CSD with Fault tolerant Full Adder. The ordinary full adder performs addition of bits, but it is not able to detect and correct whenever the faults occurred during the operation. The proposed Fault tolerant Full Adder in CSD play important role to detect the faults with their exact location and also tolerate the faults . In this paper, we present high speed, FPGA fabric aware pipelined architectures for CSD recoding circuits using fault tolerant Full Adder starting from a two’s complement number to redundant signed digit input.

Canonic signed digit; redundant signed digit; FPGA; carry chain, DFT (design for testability), double fault, Fault tolerance, Full adder, Verilog, Xillinx14.5.

"A NOVEL DESIGN OF CSD RECODING WITH FAULT TOLERANT FULL ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.86-92, April-2019, Available :http://www.jetir.org/papers/JETIR1904Q17.pdf

"A NOVEL DESIGN OF CSD RECODING WITH FAULT TOLERANT FULL ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp86-92, April-2019, Available at : http://www.jetir.org/papers/JETIR1904Q17.pdf