• 1Anil Singh
• Manish Kumar

A new hybrid energy efficient 1-bit full adder is presented in this paper which utilizes feedback loop-based circuit to enhance performance of the 1-bit full adder. The proposed circuit is designed for low delay and power dissipation thereby enhancing overall performance of the adder. The proposed work utilizes feedback-loop based XOR and MOD-GDI (Modified Gate Diffusion Input) technique which requires only 14 transistors. The design is simulated using 180nm MentorGraphics Eldo simulation tool. Simulation results show an improvement of 67% in power dissipation and 2% in PDP ( at 1.0V). Further an improvement of 91% and 85% improvement is observed in power dissipation and PDP (at 5V) respectively.

Full Adder, Power, Delay, Power-Delay Product (PDP).

"Feedback Loop based Energy Efficient Hybrid 1-bit Full Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.157-159, April-2019, Available :http://www.jetir.org/papers/JETIR1904Q29.pdf

"Feedback Loop based Energy Efficient Hybrid 1-bit Full Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp157-159, April-2019, Available at : http://www.jetir.org/papers/JETIR1904Q29.pdf