• Dr. Ramesh Pawase
• Bajirao Jawale

The Phase Locked Loops being the most important block of signal generation that is used in most of the radio and telecommunication systems. The stable and consistent signal generation with constant peak amplitude and frequency is expected feature of PLL that is achieved through FPAA experimentation. Configurable analog blocks are used for simulation subsequently hardware implementation is completed in this research project and performance evaluation of resources usage is done. It is found that 30% CABs are utilized only from FPAA1 whereas 43% CABs are utilized from FPAA2. The developed chip consumes power of 222.67 mW which is significantly minimum.

FPAA, PLL, Hardware Implementation

"Hardware Implementation and performance evaluation of PLL in FPAA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.56-61, April-2019, Available :http://www.jetir.org/papers/JETIR1904W10.pdf

"Hardware Implementation and performance evaluation of PLL in FPAA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp56-61, April-2019, Available at : http://www.jetir.org/papers/JETIR1904W10.pdf