• G. Sam Temdulkar
• N. Vamsi Praveen
• Dr.M. Janardana Raju

Today the stipulation for system on chip (SOC) for high performance applications like communications, digital signal processing etc is leading growth in present digital world. There are some requirements for high performance like reducing the area, or reducing the delay or reducing the power as area, power and delay are the important concerns in VLSI. To meet these requirements the use of smallest possible logical depth is used. As these parameters plays a major role in VLSI design ,when we consider he scan chain path in testing the flip-flops which are used for passing data are added with extra multiplexers which creates the more critical path delay. This may cause the performance degradation of the circuit. The multiplexers which are causing more delay are removed and the logic is replaced and generates randomness for data. This may produce some better effect in mixed mode random testing (serial and random mode). The proposed work takes advantage of scan flip-flops which presents better delay are used to design mixed mode logic by random scan chain. The random access scan flip flop controlling logic for both serial mode and random mode. This architecture of mixed mode is area efficient design.

Scan flip-flop, Serial scan test, Random access scan test, Mixed mode scan test, Low power test, Test application time, Test data volume

"Area efficient mixed mode scan chain design for systematic testing", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.169-176, May-2019, Available :http://www.jetir.org/papers/JETIR1905R25.pdf

"Area efficient mixed mode scan chain design for systematic testing", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp169-176, May-2019, Available at : http://www.jetir.org/papers/JETIR1905R25.pdf