• Saji Joseph

Requirements, challenges and the scaling trends of the memory system over the years as well as for future applications are discussed. Some promising design directions to overcome challenges posed by scaling of volatile and nonvolatile memory are reviewed. Introduction of high-density 6T SRAM cells and high mobility channel (HMC) is expected to improve the scalability of SRAM. Current 1T1C DRAM structure may extend for another few years, but the scaling may stop below 10nm. So, to continue DRAM scaling, cells with vertical gate and capacitorless DRAM cells are to be adopted. Presently, feasibility of multi-bit storage technology and multi-layer integration (MLC) are being explored for the scaling of flash memory. However, several emerging non-charge based storage memories such as FeRAM, MRAM, PCRAM, and ReRAM are also being investigated due to the difficulty in stacking too many layers in MLC.

SRAM, DRAM, flash, FeRAM, ferroelectric memory.

" CHALLENGES IN THE DOWNSCALING OF SEMICONDUCTOR MEMORY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.20-24, May-2019, Available :http://www.jetir.org/papers/JETIR1905X04.pdf

" CHALLENGES IN THE DOWNSCALING OF SEMICONDUCTOR MEMORY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp20-24, May-2019, Available at : http://www.jetir.org/papers/JETIR1905X04.pdf