• A Pullareddy

In this paper a new 12T static random access memory cell having single ended decoupled read-bit line (RBL) for low power operation and delay reduction is proposed. The RBL is precharged with the 50% of cell’s supply voltage and it can be charge and discharge based on the data stored in the SRAM cell. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. The RBL charges towards the supply voltage for read ‘1’ operation and it discharges toward the ground for the read ‘0’ operation. During the cell write operation virtual power rails have the same value of the RBL precharging level and are connected to true supply levels only during the read operation. Due to the dynamic control of virtual rails significantly reduces the RBL leakage. The proposed 12T cell in a commercial 90 nm technology is 1.37× the delay of 10T and reduces the read power dissipation by 20% than that of 10T SRAM cell.

read bit line, low power, SRAM cell, read static noise margin

"Low Power and High Speed 12T SRAM using Half-VDD Precharge", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.866-870, June-2019, Available :http://www.jetir.org/papers/JETIR1906905.pdf

"Low Power and High Speed 12T SRAM using Half-VDD Precharge", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp866-870, June-2019, Available at : http://www.jetir.org/papers/JETIR1906905.pdf