• C Kowsalya
• K PrasadBabu
• B Naga Rajesh

This paper describes implementation of 16-bit RISC processor with Floating Point mode design using Verilog Hardware Description Language (HDL). The architecture proposed is Harvard architecture having separate instruction and data memory. The important feature of proposed processor is pipelining, Floating Point Mode, Pipelining is used for improving the performance; such that the design is optimized for every clock cycle.one instruction is executed per clock. The instruction set finalized consists of 16 instructions, which is very compact, simple and easy to learn, which another key feature of the design is. The processor has ALU, Instruction Memory, Data Memory, Program Counter, Eight 16bit general purpose registers, Floating Point Adder/Substractor, 4-bit flag register and priority based three vectored interrupts. The processor code is synthesized for Xilinx Spartan 3A Starter Board FPGA.

RISC, HDL, FPGA, Verilog, Xilinx, Spartan, Harvard, ALU

"FPGA Implementation of Pipelined 16-bit RISC Processor with Floating Point Unit ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.105-109, June-2019, Available :http://www.jetir.org/papers/JETIR1906B14.pdf

"FPGA Implementation of Pipelined 16-bit RISC Processor with Floating Point Unit ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp105-109, June-2019, Available at : http://www.jetir.org/papers/JETIR1906B14.pdf