• MULLAPUDI CHINNI KRISHNA
• Mr.P.V.S.R.BHARADWAJA

Adaptive Clock-Gating (ACG) and Merging Flip-Flops in which several FFs are grouped and share a common clock driver are two effective low-power design techniques. Combining these techniques into a single grouping algorithm and design flow enables further power savings. We study MBFF multiplicity and its synergy with FF data-to-clock toggling probabilities. A probabilistic model is implemented to maximize the expected energy savings by grouping FFs in increasing order of their data-to-clock toggling probabilities. The clock signal driving a FF is disabled when the FFs state is not subject to change in the next clock cycle. Data-driven gating is causing area and power overheads that must be considered. In an attempt to reduce the overhead, it is proposed to group several FFs to be driven by the same clock signal, generated by ORing the enabling signals of the individual FFs. Pseudorandom bit generators (PRBGs) are widely used in many electronic equipment, thus many researchers are proposing novel solution addressed to improve the inviolability performances required in cryptographic applications. LFSR is the most used topology to implement PRBG.

Clock gating (CG), clock network synthesis, low-power design, Merging flip-flop.

"A Novel Design of Merging Flip-Flop With Adaptive Clock Gating", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.486-490, June-2019, Available :http://www.jetir.org/papers/JETIR1906F75.pdf

"A Novel Design of Merging Flip-Flop With Adaptive Clock Gating", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp486-490, June-2019, Available at : http://www.jetir.org/papers/JETIR1906F75.pdf