• ELLASAMUDRAM DURGA
• Dr.P. NAGARAJAN

Many pass-transistor logic families have been presented as of now, however no methodical synthesis technique which doesn't take signal strength on circuit execution into consideration. In the pass transistor logic, a Karnaugh based strategy which productively synthesized Pass Transistor Logic (PTL) circuits, that have adjusted loads on original and correlative complemented input signals was created. The technique was applied to the fundamental two-input and three-input logic gates in Complementary Pass Transistor Logic (CPL), Double Pass Transistor Logic (DPL) and Dual Value Logic (DVL). These techniques were general and can be reached out to blend any pass-transistor organize which expended more power[1]. In this undertaking, Complementary Pass Transistor logic is utilized which contains just NMOS transistor to construct 2-4 Decoder circuits[1]. Decoder based CPL is utilized to configuration low power memories. Use of memories is to store the data and it is one of the moderate of processor and outer interface. Since CPL is being utilized, the power is decreased. CPL based decoder for memories is planned and its performance measurements of rapid and low power is analyzed utilizing MICROWIND Tool. The proposed design of CPL is to reduce the transistor count and also achieve the better Power, area and delay performance when compared to CMOS and GDI technology based Designs.

Complementary metal–oxide–semiconductor (CMOS), Gate Diffusion Input (GDI),Pass Transistor Logic (PTL), Complementary Pass Transistor Logic (CPL), Static Random Access Memory (SRAM)

"A NOVEL DESIGN OF A LOW POWER AND AREA EFFICIENT LINE DECODER ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.593-600, June 2019, Available :http://www.jetir.org/papers/JETIR1906H62.pdf

"A NOVEL DESIGN OF A LOW POWER AND AREA EFFICIENT LINE DECODER ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp593-600, June 2019, Available at : http://www.jetir.org/papers/JETIR1906H62.pdf