• P Rishitha
• P Stella Bright
• S Kinnera
• D Sridhar

The fast development of versatile battery worked gadgets has made low power IC design. The SRAM units have turned into a vital part in current SOCs. For SRAM power, stability, delay and area are the real concerns. What's more, they are exchange offs to one another. In any case, all are critical and should be in worthy range. CMOS SRAM cell is less power devouring and have less perused and compose time. Higher cell proportions can diminish the read and compose time and enhance security. PMOS transistor with less width diminishes the power utilization. Traditional SRAM cell plans are control eager and poor entertainers in this new time of quick portable processing. In this paper, low power SRAM cell plans have been broke down for power utilization, compose delay and compose control defer item. These plans are contrasted and the ordinary 6T SRAM, 7T SRAM, 9T SRAM cells. In this paper we mostly focused on power and security and we planned an upgraded proposed 10T-SRAM cell for low power utilization.

10T SRAM, 9T SRAM, 7T SRAM, 6T SRAM

"IMPLEMENTATION OF LOW POWER MEMORY CELLS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.906-912, June 2019, Available :http://www.jetir.org/papers/JETIR1906I10.pdf

"IMPLEMENTATION OF LOW POWER MEMORY CELLS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp906-912, June 2019, Available at : http://www.jetir.org/papers/JETIR1906I10.pdf