• Shishu

Digital system implemented by using conventional gates like AND and OR gates dissipates a major amount of energy in the form of bits which gets erased during logical operations. This problem of energy loss can be solving by using reversible logic circuits in place of conventional circuits. This problem of energy loss can be solving by using reversible logic circuits in place of conventional circuits. Reversible logic is widely being considered as the potential logic design style for implementation in modern nanotechnology and quantum computing. Reversibility has become the most promising technology in digital circuits designing. In this paper proposed comparator, decoder and multiplier design methodologies for the reversible realization of reversible 16 bit adder where the designs are based on the Peres gate. The proposed design is implemented on SPARTEN3 FPGA board and is synthesized using Xilinx ISE software.

AND, OR, SPARTEN3, FPGA, Xilinx, Reversible, Decoder

"An Efficient Design and Analysis of Combinational Circuits Using Reversible Decoder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.633-638, June 2019, Available :http://www.jetir.org/papers/JETIR1906J25.pdf

"An Efficient Design and Analysis of Combinational Circuits Using Reversible Decoder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp633-638, June 2019, Available at : http://www.jetir.org/papers/JETIR1906J25.pdf