• P. Bhavya

A Novel 16-transistor static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single ended with dynamic feedback control SRAM cell enhances the Static Noise Margin for ultra low power supply an equalized bit line scheme to eliminate the leakage dependent on data pattern and thus improves RBL sensing . The design is to reduce the circuit complexity level and strom consumption level. The architecture contains sleep transistor which is used to reduce outflow power when these operate in “stand by mode “ due to inefficient passing of the voltage.

Ooze reduction, Semiconductor Memory

"16T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.734-738, June 2019, Available :http://www.jetir.org/papers/JETIR1906R02.pdf

"16T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp734-738, June 2019, Available at : http://www.jetir.org/papers/JETIR1906R02.pdf