• Himanshu Shekhar

In the era of microelectronics, rate of chip disappointment is expanded with expanded in chip thickness. A framework must be fault tolerant to diminish the disappointment rate. The nearness of various faults can obliterate the usefulness of a full adder and there is an exchange off between number of fault endured and zone overhead. This paper displays a territory productive fault tolerant full adder plan that can fix single and twofold fault without intruding on the normal task of a framework. RTL amalgamation has been finished by utilizing Xilinx 14.7 and recreation is finished by utilizing Xilinx Isim. In this work we used to identify the fault dependent on interior usefulness by utilizing oneself checking full adder and pipeline idea. By the proposed work of fault endured we can get compelling outcomes as far as Region, Delay, Power utilization angles and number of fault endured when contrasted with the current designs

Single fault, double fault, self checking adder, self repairing, fault tolerant, Adder

"Implementation of double fault tolerant full adder using fault localization with pipelining ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.25-30, June 2019, Available :http://www.jetir.org/papers/JETIR1906R41.pdf

"Implementation of double fault tolerant full adder using fault localization with pipelining ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp25-30, June 2019, Available at : http://www.jetir.org/papers/JETIR1906R41.pdf