• TIRUPATI B. YADAV
• DEVENDRA S. CHAUDHARI

Arithmetic and Logic Unit (ALU) is the most crucial and core component of central processing unit which consists of many computational units like adders, multipliers, logical units, etc. Real time applications such as controlling environmental conditions demand quick response of the processor for processing. The vedic mathematics consists of many sutras which can be used for improving speed with reduced component requirements and delay. It accomplishes arithmetic, logic operations on integers stored in accumulator, register array, operand register and fetch value from external memory. In this paper, vedic mathematics sutra were used for enhancing the overall performance of the processor. vedic ALU was coded in VHDL using Xilinx software. The synthesis results indicated an overall improvement of about 0.539 ns for vedic over conventional 16-bit ALU.

Vilokanam, UrdhvaTiryakbhyam, Parvartaya, ALU, etc.

"IMPLEMENTATION OF ARITHMETIC LOGIC UNIT USING VEDIC MATHEMATICS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.918-924, June-2019, Available :http://www.jetir.org/papers/JETIR1906S66.pdf

"IMPLEMENTATION OF ARITHMETIC LOGIC UNIT USING VEDIC MATHEMATICS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp918-924, June-2019, Available at : http://www.jetir.org/papers/JETIR1906S66.pdf