UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1907415


Registration ID:
220180

Page Number

767-771

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Title

ERROR CORRECTION CODE FOR 32 BIT DATA WORDS WITH EFFICIENT DECODING

Abstract

In attendance late enthusiasm on structuring multi bit mistake redress (MEC) codes for 32 bit information words which supports quick interpreting for protecting the memories from soft errors. The proposed implementation presents a cost efficient technique to correct multiple bit upsets to save from harm memories against radiation. As technology scales a large number of cells are ordinarily affected by multiple cell upsets. For anticipating the adventure of MCU’s sundry error correction codes (ECC) are unremarkably used, but the main obstacle is that they demand more redundant bits, higher intricate encoder & decoder architecture then also superior latency overheads. The area and latency overheads reduced by proposing decimal matrix code(DMC) compared with obtainable hamming code, OLS codes and furthermore improves the memory dependability by uplifting the blunder remedy astuteness. In the projected article novel decimal lattice code dependent on separation-image(divide-symbol) is implemented for improving the memory dependability with lower latency overhead. The maximum mistake location and redress ability is done by using decimal algorithm utilizes by the proposed DMC. Additionally, the encoder-reuse method (ERT) is proposed to limit the territory overheads of additional circuits without exasperating the entire encoding and translating forms. DMC encoder utilized by ERT, is a piece of decoder. Along these lines it outfit for memory fashioners with an extra alternative that can be helpful when making tradeoff between memory dimension and rate The total designs are designed and synthesized in Xilinx ISE with verilog HDL coding.

Key Words

ECC, MCU, DMC, ERT.

Cite This Article

"ERROR CORRECTION CODE FOR 32 BIT DATA WORDS WITH EFFICIENT DECODING", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.767-771, June 2019, Available :http://www.jetir.org/papers/JETIR1907415.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"ERROR CORRECTION CODE FOR 32 BIT DATA WORDS WITH EFFICIENT DECODING", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp767-771, June 2019, Available at : http://www.jetir.org/papers/JETIR1907415.pdf

Publication Details

Published Paper ID: JETIR1907415
Registration ID: 220180
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 767-771
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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