• Ayushi Nagar
• Prof. Rahul Shrivastava

CMOS is an innovation for developing coordinated circuits. CMOS innovation is utilized in chip, microcontrollers, static Smash, and other computerized rationale circuits. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. A transmission gate based FF (TGFF) design is used most widely, due to its fully static operation, robust voltage scaling, and none data contention. However, a major drawback of TGFF is the excessive working load to the clock signal, which leads to considerably dynamic power even in low or zero switching activity. This paper is presenting an Efficient design of true single phase clocking based trusted storage in CMOS..

TSPC, VLSI, Flip-Flop, Clock, RAM,ROM,SRAM,DRAM

"Performance Improvement in Ultra-Low Power 18-Transistor Single-Phase Clocked Flip-Flop in CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.350-354, June 2019, Available :http://www.jetir.org/papers/JETIR1907806.pdf

"Performance Improvement in Ultra-Low Power 18-Transistor Single-Phase Clocked Flip-Flop in CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp350-354, June 2019, Available at : http://www.jetir.org/papers/JETIR1907806.pdf