• P.PUSHPALATHA
• Gunupuram Taruna Kumari

In multiplier less FIR filter, tremendous effects came into existence to minimize the adders which are present in the multiplier block, for the sake of reducing total area of chip and consumption of power. If the adder’s quantity in multiplier block is less in number then there is no need to minimize the power consumed in a FIR circuit. Here comes a power oriented method of optimization in a linear phase finite impulse response filter used in our system. In search of discrete coefficient algorithm, we use the power index which has the average adder depth in structural adders. The existing systems techniques uses transposed form configuration, the drawback are less efficiency and area complexity. Instead the adders search of coefficients pairs which minimizes adders, in order to get coefficients pair that reduces the AAD addition adder depth of SA’s structural adders. By using stable and reconfigurable applications they are developed to find discrete coefficient. As a result, area complexity reduces with increases performance and high efficiency is obtained .XILINX system generator toolbox is required for circuit implementation.

Transposed form FIR, multiple constant multiplication (MCM), Low power, block processing, VLSI.

"Utilization of Low Power Linear-Phase FIR filter for Reconfigurable Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.458-463, June 2019, Available :http://www.jetir.org/papers/JETIR1907822.pdf

"Utilization of Low Power Linear-Phase FIR filter for Reconfigurable Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp458-463, June 2019, Available at : http://www.jetir.org/papers/JETIR1907822.pdf