• G.C.Arun Kumar
• Dr.K.Mahalakshmi

Power management (PM) in System on Chip (SoC) plays a crucial role in mobile device architectures. Several new architectures were proposed to reduce the power inside the IPs (Intellectual property) like clock gating and power gating, with the task of reducing system level IDLE power gating. According to the nature of the system , multiple system states are created based on power and IDLE conditions such as ’P states ’ and ’C states’. In order to power down the circuit further, it has to go to a deeper state, but in order to achieve this we need to do power gating in various regions of the circuit. As a consequence when the system goes through various power up sequences, the wake up latency will be much bigger which affects the system performance. In order to combat this situation, alternate clock sources were introduced such as a ring oscillator clock. Since the ring oscillator clock is susceptible to Process, Voltage and Temperature (PVTA) variations, a innovative way to reduce the system latency by a new power architecture flow with a calibrated ring oscillator clock that runs all power management operations on the newly generated clock is introduced. The main goal of this design is to reduce the system latency while being more resistant to PVTA variations.

CRO, Power Management, Power Gating, Save- Restore, PVTA, RTC, IP.

"Improvement of Performance in Architecture of Ring Oscillator Clock Generation using CPG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.735-741, June 2019, Available :http://www.jetir.org/papers/JETIR1907859.pdf

"Improvement of Performance in Architecture of Ring Oscillator Clock Generation using CPG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp735-741, June 2019, Available at : http://www.jetir.org/papers/JETIR1907859.pdf