UGC Approved Journal no 63975(19)

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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1907867


Registration ID:
220817

Page Number

782-787

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Title

Efficient Area and Delay of Error Avoidance Technique using Synchronizer and Flip-flops

Abstract

Time borrowing techniques have been widely used to mitigate the timing errors in high-performance designs. The dynamic flip-flop conversion technique is introduced by Ahmadi et al. which dynamically converts flip-flops into transparent latches to grant the time borrowing from the next stage and prevent setup time violation but it could not prevent the timing violation in the successive critical path (SCP) and critical feedback path (CFP) structures. Then a fast prediction logic of the critical path along with dynamic clock stretching in SCP and CFP structures was introduced which also could not prevent the timing errors. The proposed technique uses glitch free clock switching for unrelated clocks which is more effective in terms of the performance improvement and less area utilization when compared with the best existing technique. The designs are modelled in Verilog HDL and are functionally verified by using Xilinx ISIM Simulation Tool. The designs are synthesized for Spartan3E FPGA by suing Xilinx ISE 14.5 Tools for the device XC3S500E with a package of FG320 and a speed grade of -5. The proposed design proves to be better than the remaining designs functionally. Also the proposed design occupies an area which is around 33% less than the previous designs.

Key Words

Dynamic clock stretching, high-performance design, prediction logic, setup time violation, time borrowing

Cite This Article

"Efficient Area and Delay of Error Avoidance Technique using Synchronizer and Flip-flops", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.782-787, June 2019, Available :http://www.jetir.org/papers/JETIR1907867.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Efficient Area and Delay of Error Avoidance Technique using Synchronizer and Flip-flops", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp782-787, June 2019, Available at : http://www.jetir.org/papers/JETIR1907867.pdf

Publication Details

Published Paper ID: JETIR1907867
Registration ID: 220817
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 782-787
Country: CHITTOOR, ANDHRA PRADESH, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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